The present invention relates to a data processing system and a method of interconnect arbitration.
With the increasing availability and success of portable devices like PDA, notebooks, mobile phones, portable MP3-player etc. the power consumption of these devices has become more and more important within modem integrated circuits and the design thereof and a considerable amount of investigation and design efforts have been conducted to reduce the power consumption. As the VLSI design of ICs used in such devices is shifting into the nanometer domain, the energy which is dissipated by the interconnect in a system-on-chip becomes a significant part of the overall system power consumption. Furthermore, a limiting factor for reducing the weight and size of portable devices correlate to the amount of batteries which are required to provide the power dissipated by the electronic circuits within the portable devices.
The power consumption of the interconnect, i.e. the bus or the network, is not only based on the physical properties of the interconnect, like the voltage swing, the wire delay, the topography of the interconnect or the like, but also on the data flow in the system-on-chip, i.e. the processor-processor communication and the processor-memory communication. This communication can be of the following origins: cache and memory transactions (data fetch from shared memory), cache coherence operations (updated data in a shared memory must be updated in all cache copies resulting in synchronization traffic), packet segmentation overheads (segmenting dataflow into packets will introduce an additional data overhead) or contentions between packets (re-routing packets in case of a contention).